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[VHDL-FPGA-Verilog] FFT

Description: verilog 实现FFT IP核的控制，借鉴给需要学习的朋友-verilog achieve FFT IP core control, reference to the need to learn a friend
Platform: | Size: 12124160 | Author: 甘超 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 采用verlog编写的tlc5615驱动程序，并利用了rom核实现了dds功能-Using verlog written tlc5615 driver, and use the rom-core functions to achieve a dds
Platform: | Size: 619520 | Author: ranshaoqiang | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM_IP_core

Description: DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Platform: | Size: 474112 | Author: zyy | Hits:

[VHDL-FPGA-Verilog] USB_IP-CORE-design

Description: USB2.0的IP核，需要添加额外的PHY模块，使用Verilog语言编写-USB2.0 IP core, you need to add additional PHY module, using the Verilog language
Platform: | Size: 201728 | Author: 董剑 | Hits:

[VHDL-FPGA-Verilog] Axi_mux

Description: The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.
Platform: | Size: 41984 | Author: Paul Stephen | Hits:

[VHDL-FPGA-Verilog] dma_0

Description: SOPC系统编译的DMA的Verilog代码-DMA IP core in SOPC
Platform: | Size: 5120 | Author: zy | Hits:

[VHDL-FPGA-Verilog] can_latest.tar

Description: 用Verilog写的CAN协议IP核 已经验证可以使用 -CAN protocol written in Verilog IP core has been verified using
Platform: | Size: 1172480 | Author: 薛鹏举 | Hits:

[VHDL-FPGA-Verilog] FIFOED_UART

Description: CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
Platform: | Size: 6144 | Author: 杨胜尧 | Hits:

[VHDL-FPGA-Verilog] 8051core-Verilog

Description: 可以在FPGA上，实现80C51的软核，经过验证-In the FPGA to realize the soft-core 80C51, proven
Platform: | Size: 52224 | Author: Colin | Hits:

[VHDL-FPGA-Verilog] mpci32-verilog

Description: 一个32BIT 33/66MHz PCI CORE，verilog 的RTL CODEs-pci ipcore writen by verilog
Platform: | Size: 722944 | Author: 刘华 | Hits:

[VHDL-FPGA-Verilog] Manchester-Encoding-Verilog

Description: THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise. -THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise.
Platform: | Size: 8192 | Author: liyapei | Hits:

[VHDL-FPGA-Verilog] zigbee_sensor

Description: ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。 在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信） -ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear quartusII inside, using the serial port with the main control machine communication, access to the sensor from the control on the temperature, humidity, photoresistors, thermistors, and other information (including the main control machine from the control machine by zigbee protocol communications)
Platform: | Size: 1388544 | Author: | Hits:

[VHDL-FPGA-Verilog] IP-coreincluding-VHDL-and-Verilog

Description: 芯片设计必须解剖的IP核（包含VHDL和Verilog代码）-The IP core chip design must anatomy (including VHDL and Verilog code)
Platform: | Size: 1180672 | Author: 张磊 | Hits:

[VHDL-FPGA-Verilog] LIP1711CORE_system_gpio

Description: LIP1711 GPIO System Core Verilog source code
Platform: | Size: 4868096 | Author: jc | Hits:

[VHDL-FPGA-Verilog] verilog-ip-core

Description: verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
Platform: | Size: 3798016 | Author: 刘兵 | Hits:

[VHDL-FPGA-Verilog] 8051core-Verilog

Description: 用verilog在FPGA内部实现8051内核，超好、超难找的资料！共享出来！-Verilog FPGA internal 8051 core, super, super hard to find! Shared out!
Platform: | Size: 52224 | Author: 于祥龙 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM-Verilog-HDL-IP-CORE

Description: ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
Platform: | Size: 74752 | Author: shen jun | Hits:

[VHDL-FPGA-Verilog] Altera-SDRAM_controller-IP-CORE

Description: ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
Platform: | Size: 2378752 | Author: mr jiang | Hits:

[VHDL-FPGA-Verilog] verilog

Description: it is xilinx SDR SDRAM controller core
Platform: | Size: 297984 | Author: roger1 | Hits:

[VHDL-FPGA-Verilog] 8051core-Verilog

Description: Verilog实现8051 core.基本可用，基于Altera硬件平台实际验证通过。-how to implement 8051 core via verilog.
Platform: | Size: 52224 | Author: wetta | Hits:
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